In addition to the text terminal used to invoke the program, Electric uses a color display with a mouse as a work station. Separate windows are used for text and graphics.
If a library disk file is mentioned on the command line, that file is read as the initial design for editing. In addition, the following switches are recognized:
Collections of nodes and arcs can also be aggregated into facets of cells which can be used higher in the hierarchy to act as nodes. These user-defined nodes have ports that come from internal nodes whose ports are exported. Facets are collected in libraries which contain a hierarchically consistent design.
Arcs have properties that help constrain the design. For example, an arc may rotate arbitrarily or be fixed in their angle. Arcs can also be stretchable or rigid under modification of their connecting nodes. These constraints propagate hierarchically from the bottom-up.
The nMOS technologies have arcs available in Metal, Polysilicon, and Diffusion. The primitive nodes include normal contacts, buried contacts, transistors, and "pins" for making arc corners. Transistors may be serpentine and the pure layer nodes may be polygonally described with the node trace command. The "nmos" technology has the standard Mead&Conway design rules.
The CMOS technologies have arcs available in Metal, Polysilicon, and Diffusion. The Diffusion arcs may be found in a P-well implant or in a P+ implant. Thus, there are two types of metal-to-diffusion contacts, two types of diffusion pins, and two types of transistors: in P-well and in P+ implant. As with nMOS, the transistors may be serpentine and the pure layer primitives may be polygonally defined. The "cmos" technology has the standard design rules according to Griswold; the "mocmos" technology has design rules for the MOSIS CMOS process (double metal); the "mocmossub" technology has design rules for the MOSIS CMOS Submicron process (double poly and up to 6 metal); the "rcmos" technology has round geometry for the MOSIS CMOS process.
The "schematic" technology provides basic symbols for doing schematic capture. It contains the logic symbols: BUFFER, AND, OR, and XOR. Negating bubbles can be placed by negating a connecting arc. There are also more complex components such as flip-flop, off-page-connector, black-box, meter, and power source. Finally, there are the electrical components: transistor, resistor, diode, capacitor, and inductor. Two arc types exist for normal wires and variable-width busses.
The "artwork" technology is a sketchpad environment for doing general-purpose graphics. Components can be placed with arbitrary color and shape.
The "generic" technology exists for those miscellaneous purposes that do not fall into the domain of other technologies. It has the universal arc and pin which can connect to ANY other object and are therefore useful in mixed-technology designs. The invisible arc can be used for constraining two nodes without making a connection. The unrouted arc can be used for electrical connections that are to be routed later with real wires. The facet-center primitive, when placed in a facet, defines the cursor origin on instances of that facet.
The hierarchical checker looks all the way down the circuit for all design-rules. Another option allows an input deck to prepared for ECAD's Dracula design-rule checker.
In preparation for most simulators, it is necessary to export those ports that you wish to manipulate or examine. You must also export power and ground ports.
In preparation for SPICE simulation, you must export power and ground signals and. explicitly connect them to source nodes. The source should then be parameterized to indicate the amount and whether it is voltage or current. For example, to make a 5 volt supply, create a source node and set the SPICE card to: "DC 5". Next, all input ports must be exported and connected to the positive side of sources. Next, all values that are being plotted must be exported and have meter nodes placed on them. The node should have the top and bottom ports connected appropriately.
There are two stitching modes: auto stitching and mimic stitching. In auto stitching, all ports that physically touch will be stitched. Mimic stitching watches arcs that are created by the user and adds similar ones at other places in the facet.
Steven M. Rubin Static Free Software 4119 Alpine Road Portola Valley, Ca 94028 Also a cast of thousands: Philip Attfield (Queens University): Polygon merging, facet dates Ron Bolton (University of Saskatchewan): Miscellaneous help Mark Brinsmead (Calgary): Apollo porting Stefano Concina (Schlumberger): Polygon clipping Peter Gallant (Queen's University): ALS simulation T. J. Goodman (University of Canterbury) TEXSIM simulation D. Guptill (Technical University of Nova Scotia): X-window interface Robert Hon (Columbia University): CIF input Sundaravarathan Iyengar (Case Western Reserve University): nMOS PLA generator Allan Jost (Technical University of Nova Scotia): X-window interface Wallace Kroeker (University of Calgary): Digital filter technology, CMOS PLA generator Andrew Kostiuk (Queen's University): QUISC 1.0 Silicon compiler Glen Lawson (S-MOS Systems): GDS-II input David Lewis (University of Toronto): Short circuit checker John Mohammed (Schlumberger): Miscellaneous help Mark Moraes (University of Toronto): X-window interface Sid Penstone (Queens University): many technologies, GDS-II output, SPICE improvements, SILOS simulation, GENERIC simulation J. P. Polonovski (Ecole Polytechnique, France): Memory management improvement Kevin Ryan (Technical University of Nova Scotia): X-window interface Nora Ryan (Schlumberger): Technology translation, Compaction Brent Serbin (Queen's University): ALS Simulator Lyndon Swab (Queen's University): Northern Telecom CMOS technologies Brian W. Thomson (University of Toronto): Mimic stitcher, RSIM interface Burnie West (Schlumberger): Network maintainer help, bipolar technology Telle Whitney (Schlumberger): River router Rob Winstanley (University of Calgary): CIF input, RNL interface Russell Wright (Queen's University): Lots of help David J. Yurach (Queen's University): QUISC 2.0 Silicon compiler
|~/.cadrc||Personal startup file|
|~/electric.log||Session logging file|
|*.elib||Binary input/output files|
|*.txt||Text input/output files|
|*.cif||CIF input/output files|
|*.pla||PLA personality input files|
|*.map||Color map files|
|*.sim||ESIM, RSIM, RNL, and COSMOS simulation output|
|rsim.in||RSIM simulation binary output|
|rnl.in||RNL simulation binary output|
|*.spi||SPICE simulation output|
|*.ver||VERILOG simulation output|
|*.ntk||MOSSIM simulation output|
|*.sil||SILOS simulation output|
|*.tdl||TEXSIM simulation output|
|*.pal||ABLE PAL simulation output|
|/usr/local/bin/findfastshorts||Fast short circuit checker|
|/usr/local/bin/fastshorts||Slow short circuit checker|
|/usr/local/bin/esim||Switch level simulator: ESIM|
|/usr/local/bin/rsim||Switch level simulator: RSIM|
|/usr/local/bin/rnl||Switch level simulator: RNL|
|/usr/local/bin/presim||RNL and RSIM pre-filter|
|/usr/local/bin/spice||Circuit level simulator: SPICE|
|/usr/local/electric/lib/nl.l||RNL startup file|